New lyout design for submicron CMOS output transistors to improve drivign capabiltiy and ESD robustness

摘要

New layout design to effectively reduce the layout area of CMOS output transistors but with higher driving capability and better ESD reliability is proposed. The output transistors of large device dimensions are assembled by a plurality fo the basic layout cells, which have the square, hexagonal or octagonal shapes. The output transistors realized by these new layout styles have more symmetrical device structures, which can be more uniformaly triggered during hte ESD-stress events. With theoreteicla calculation and experimental verification, both higher output driving/sinking current and stronger ESD robustness of CMOS ouptput buffers can be practically achieved by the proposed new layout styles withoin a smaller layout area in the non-silicided buld CMOS process. The output transistors assembled by a plurality of the proposed layout cells also have a lower gate resistance and a smaller drain capacitance than that realized by the traditional finger-gype layoutl.