Improving avalanche robustness of SiC MOSFETs by optimizing three-region P-well doping profile

摘要

Avalanche robustness in dynamic operation is one of the main obstacles to further promote the commercialization of SiC MOSFETs. In this paper, a cell-level optimization design is proposed to suppress the avalanche failure caused by parasitic BJT activation. Several retrograde doping profiles with different thickness of lightly doping region (TLD) are designed for P-well, which is the key area affecting the avalanche failure. The analytical calculations and TCAD simulations show that as the TLD increases, the on-resistance decreases and the possibility of BJT activation increases. The TLD slightly larger than the thickness of the N+ can achieve a better avalanche capability without obvious degradation of the conduction characteristics. Besides, increasing the concentration of the retrograde P-well heavily doping region can improve the avalanche capability, but reduce the blocking voltage. This contradiction can be alleviated by adding a low-doped region at the bottom of the P-well to form a three-region P-well doping profile. This three-region P-well doping profile can achieve a significant improvement in the avalanche capability without degrading the conduction characteristic and blocking capability of the device, which provides meaningful guidance for the design of high avalanche robustness devices.