CSME: A novel cycle-sensing margin enhancement scheme for high yield STT-MRAM

摘要

Spin-transfer torque (STT)-magnetic random access memory (MRAM) requires yield-aware design for hybrid magnetic-CMOS integration. In this paper, a novel cyclesensing margin enhancement (CSME) scheme with pMOS assisted voltage-type sense amplifier (p-VSA) is proposed to alleviate imperfect process induced performance fluctuations. With iterated charging-discharging through non-volatile data path and reference path, read margin can be significantly improved thanks to the enlarged sensing window. Simulation is performed using MTJ compact model and an industrial 28-nm CMOS process. Results show that with 0.6 V supply voltage similar to 14.1% read yield improvement can be realized at 50% tunnel magnetoresistance (TMR) ratio comparing to conventional VSA.