Real-time soft error testing system for large-area QDR Ⅱ + SRAM array on the Tibetan Plateau

摘要

In this study, a real-time testing system consisting of a large-area array of 72 QDR II + SRAMs (larger than 10-Gbit manufactured in 65 nm CMOS technology) was developed and assembled on the Tibetan Plateau at an altitude of 4300 m. A new topological structure with 9 QDR II + devices operating synchronously by a single FPGA was proposed and the signal integrity of the large-area high-speed QDR II + SRAMs was solved. Under harsh natural radiation conditions, the complex and expensive system monitored a large number of devices in parallel for 153 days uninterruptedly. 43 soft errors including single bit upsets (SBUs), multiple-cell upsets (MCUs), single event induced hard errors (SHEs) and burst errors were observed, with a calculated SER value of 2356 FIT/Mb. Meanwhile, these results effectively validated the testing system.