On-chip ESD protection design for integrated circuits : an overview for IC designers

摘要

This tutorial paper reviews the state of knowledge of on-chip ESD (electrostatic discharging) protection circuit design for integrated circuits. The discussion covers critical issues in ESD protection design, i.e. ESD test models, ESD fai]ure mechanisms, ESD protection structures, ESD device modeling, ESD simulation, ESD layout issues, and ESD--to--circuit interactions, etc. This review serves to provide practical IC designers with a thorough and heady reference in dealing with complex ESD protection design for integrated circuits.