An analytical 2D model for drain-induced barrier lowering in subquarter micrometer gate length InAlAs/InGaAs/InAlAs/InP LMHEMT

摘要

This paper presents an analytical 2D model for InAlAs/InGaAs/InAlAs/InP LMHEMT that explains the drain induced barrier lowering (DIBL) and its effect on the device performance. The increasing drain voltage lowers the potential barrier between source and drain in or near the subthreshold region. As the barrier is lowered to be comparable to the thermal energy the device begins to conduct again. This effect causes the threshold voltage control problem and degrades the device performance. The model is used to obtain the potential distribution and the electric field in the depletion region and the threshold voltage is also calculated form the minimum channel potential. It is proposed as a consequence of the analysis that the device degradation due to DIBL effect is a very short channel problem.