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机译:DG FinFET具有对称,不对称,束缚和独立栅极选项以及电路协同设计的超低功耗亚阈值逻辑的鲁棒性比较
Micro Electronics and VLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology Roorkee, Roorkee 247667, India;
Micro Electronics and VLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology Roorkee, Roorkee 247667, India;
Shobhit University, Meerut-250110, Uttarpradesh, India;
circuit topologies; device/circuit co-design; DG FinFETs; symmetric DGMOSFET; asymmetric DGMOSFET; tied gate DGMOSFET; independent gate DGMOSFET; subthreshold logic; ultra low power;
机译:具有对称,非对称,3T,4T DGFinFET的强大,超低功耗亚阈值逻辑电路
机译:亚阈值逻辑的器件和电路协同设计鲁棒性研究,用于32 nm CMOS超低功耗应用
机译:具有捆绑独立栅极和对称非对称选项的下叠式DGMOSFET的亚阈值电流和亚阈值摆幅的分析模型
机译:超低功耗亚阈值逻辑的3T-4T DG-FinFET的鲁棒性和性能比较研究
机译:强大的超低功耗亚阈值数字电路设计。
机译:用于低功耗逻辑电路的双Vth独立栅极FinFET
机译:多阈值空间常规逻辑在超低功耗自适应波束形成电路中的应用。