An implementation of a new 11-bit 1.2 GS/s hybrid DAC with a noval 3-bit Sub-DAC

摘要

this brief presents a new 11-bit 1.2 GS/s hybrid digital to analog converter (DAC) simulated in 65 nm CMOS technology. In this new structure, a combination of a resistor ladder and current sources is used to realize the 11-bit DAC structure. The current sources are connected to different nodes of the resistor ladder in a logical way. In this situation, equal current sources make different voltage values. Furthermore, the complicated binary to thermometer decoders are exchanged with the basic digital logics. This new technique remarkably reduces the number of current sources needed for realization an 11-bit DAC and leads to the circuit dissipates just 4.68 mW power while the power supply is 1.2 V. Also, the occupied area is 0.0061 mm(2). Post layout simulation results indicate that the spurious-free dynamic range (SFDR) is more than 70 dB over 600 MHz Nyquist BW. The INL and DNL parameters are also obtained better than 1.2 LSB and 1 LSB, respectively.