A novel dual loop adaptive equalizer based on spectrum balancing technique

摘要

Inductorless circuits are gaining advantage in RF and high-speed serial link circuits due to the reduced silicon area. This paper presents an inductor-less adaptive equalizer featuring both data rate adaptation and channel loss adaptation. The conventional adaptive equalizers use spectrum balancing technique. The spectrum balancing technique balances the power in low and high frequency components with cutoff frequency of the filters as 0.28/(Tb)(T-b is the minimum bit period of the incoming data stream). The proposed technique removes the necessity of using high pass filter and uses only a programmable low-pass filter in the adaptive equalization loop. This technique leads to the tunability of the equalizer over a wide range of throughput and channel losses. For the proof of concept, the entire equalizer circuit is designed and fabricated in 180 nm mixed mode CMOS technology. The measurements with lossy channels show that the proposed adaptive equalizer is able to work well for the channel losses up to 6 dB and wide throughput of 1-3.125 Gbps. The design is targeted to operate at a maximum data rate of 3.125 Gbps to meet JESD 204 standards. The proposed adaptive equalizer consumes a power of 9.8 mW/Gbps including 10 buffers.