A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology

摘要

The demand for high-performance analog-to-digital converters is pushing toward the utilization of small dynamic comparators with low power consumption, low offset voltage, high speed, and independent input common-mode voltage. In this paper, a new high-speed dynamic comparator is presented, which its delay time is decreased compared to conventional dynamic comparators. In the suggested comparator, a complementary differential pair is utilized in the input to improve the offset voltage and comparison speed. The equations related to the delay time and input referred offset voltage of the proposed structure are derived, and the effective parameters to reduce them are identified. The post-layout simulation results in 65 nm CMOS technology demonstrate that the clock frequency of the proposed comparator can be 6 GHz while the delay time is 42.7 ps. The power consumption is 381 mu W when the proposed comparator is supplied with 1.2 V. Also, the occupied area is 141.7 mu m(2).