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首页> 外文期刊>Microelectronic Engineering >Improved programming and erasing speeds of poly-Si flash memory device by HfO_2/Si_3N_4 bandgap-engineered trapping layer
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Improved programming and erasing speeds of poly-Si flash memory device by HfO_2/Si_3N_4 bandgap-engineered trapping layer

机译:HfO_2 / Si_3N_4带隙工程俘获层提高了多晶硅闪存器件的编程和擦除速度

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摘要

Effects of HfO_2/Si_3N_4 bandgap-engineered trapping layer (BETL) on poly-Si flash memory device are studied for the first time. Planar and nanowire (NW) channel flash memory devices are successfully fabricated to study the effects of BETL. The programming and erasing speeds can be improved by BETL on both planar and NW channel devices, and the improvement is more obvious on NW channel devices with even a lower operation voltage. The device with BETL and NW channel demonstrates the best programming and erasing speeds due to the electric-field enhancement effect and the band-engineering in charge-trapping layer. It also shows good retention and endurance properties, which makes it promising for 3-D memory integration.
机译:首次研究了HfO_2 / Si_3N_4带隙工程陷阱层(BETL)对多晶硅闪存器件的影响。平面和纳米线(NW)通道闪存设备已成功制造,以研究BETL的影响。在平面和NW沟道器件上均可通过BETL来提高编程和擦除速度,而在工作电压更低的NW沟道器件上,这种改善更为明显。具有BETL和NW通道的器件由于电场增强效果和电荷陷阱层中的能带工程技术而具有最佳的编程和擦除速度。它还显示出良好的保留和持久性,这使其有望用于3-D内存集成。

著录项

  • 来源
    《Microelectronic Engineering 》 |2013年第9期| 17-20| 共4页
  • 作者单位

    Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, ROC;

    Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, ROC;

    Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, ROC;

    Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, ROC;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Poly-Si; Nanowire; Bandgap-engineering; HfO_2; Si_3N_4; Flash memory;

    机译:多晶硅纳米线;带隙工程;HfO_2;Si_3N_4;快闪记忆体;

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