First demonstration of device-quality symmetric N-MOS and P-MOS capacitors on p-type and n-type crystalline Ge substrates

摘要

Three significant issues with respect to the ultimate scaling limitations of CMOS devices are (ⅰ) the channel or transport material, (ⅱ) high-K compatible gate stacks: (a) the interface with the semiconductor substrate; (b) the high dielectrics, and (c) the gate metal, and (ⅲ) the topological structure, planar, nano-tube, or in, etc. Two of these are high-lighted, focusing on (i) crystalline Ge, and transition metal dielectrics including specifically non-crystalline Hf Si oxynitrides, and nano-grain (a) ultra-thin 2 nm thick HfO_2 and TiO_2. The research has demonstrated shallow trap interfacial slow trap densities of ～5 × 10~(10)cm~(-2), no detectable negative bulk fixed charges, and symmetric N- and P-MOCAPS in planar geometries. EOT values <0.5 nm were obtained for low-leakage current for N-MOSCAPS with ng-TiO_2 in contact with plasma processed c-Ge substrates.