Modeling the edge-placement yield of a cut process for self-aligned multiple patterning

摘要

Overlay errors and cut-hole critical dimension variations are serious concerns in complementary lithography that can drive the scaling of IC technology down to (half-pitch) 7 nm. Their combined effect on the edge-placement accuracy of cut holes over the 1-D grating structures is critical to the yield of spacer based self-aligned multiple patterning processes. In this paper, an edge-placement yield model for such a cut process is presented. The yield-related features are identified and a probability-of-failure function is introduced to construct the yield formula. Both overlay errors and cut-hole critical dimension variations are taken into account and the key parameters that impact the process yield are investigated. Our calculation results show that an optimal cut-hole overhang must be identified first in order to achieve the maximum yield. The scaling trend of the edge-placement yield is also studied and a non-trivial challenge is found when the half pitch of IC patterns reaches sub-10 nm.