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Wet and Siconi® cleaning sequences for SiGe p-type metal oxide semiconductor channels

机译:SiGe p型金属氧化物半导体通道的湿法清洗和Siconi®清洗顺序

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摘要

The low temperature integration of new materials (such as SiGe channels for the holes) is mandatory in advanced metal oxide semiconductor field effect transistors (i.e. in 14 nm technology node devices and beyond). In this paper, we have investigated the removal of SiGe oxides prior to Selective epitaxial Growth of Si or SiGe:B in Sources/Drains regions. A very efficient removal of contaminants (C, F, O...) is mandatory if the H-2 bake that precedes epitaxy is removed because of thermal budget constraints. As germanium is very reactive in the air, in-situ surface preparation schemes (conducted for instance in a Siconi (R) chamber) might be useful on SiGe surfaces. This way, the queue-time issues associated with "HF-Last" (HF/HCl follow by deionization water rinse) processes in single wafer wet cleaning tools are avoided. Germanium-rich SiGe layers (Si0.6Ge0.4) were used to characterize the native oxide removal efficiency of "HF-Last" and Siconi (R) processes. Then, a new surface preparation strategy was developed based on i) a wet chemical oxide formation followed by ii) a standard Siconi (R) process whose efficiency towards SiO2 has conclusively been demonstrated. Parallel Angle Resolved X-ray Photoelectron Spectroscopy was used to study the chemical composition of the native or chemical oxide and evaluate the efficiency of that treatment on carbon, germanium oxide and silicon oxide. (C) 2017 Elsevier B.V. All rights reserved.
机译:在先进的金属氧化物半导体场效应晶体管中(即在14 nm技术节点器件及更高版本中),新材料的低温集成(例如用于孔的SiGe通道)是强制性的。在本文中,我们研究了在源/漏区中选择性外延生长Si或SiGe:B之前去除SiGe氧化物的方法。如果由于热预算的限制而去除了外延之前的H-2烘烤,则必须非常有效地去除污染物(C,F,O ...)。由于锗在空气中的反应性很强,因此原位表面制备方案(例如在Siconi(R)室中进行)可能在SiGe表面上有用。这样,避免了与单晶片湿式清洁工具中的“ HF-Last”(HF / HCl之后进行去离子水冲洗)过程相关的排队时间问题。富含锗的SiGe层(Si0.6Ge0.4)用于表征“ HF-Last”和Siconi(R)工艺的天然氧化物去除效率。然后,基于以下方法开发了一种新的表面制备策略:i)形成湿法化学氧化物,其后ii)最终证明了其对SiO2的效率的标准Siconi(R)工艺。平行角分辨X射线光电子能谱用于研究天然或化学氧化物的化学组成,并评估该处理对碳,氧化锗和氧化硅的效率。 (C)2017 Elsevier B.V.保留所有权利。

著录项

  • 来源
    《Microelectronic Engineering》 |2018年第2期|84-89|共6页
  • 作者单位

    CEA, LETI, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble, France;

    CEA, LETI, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble, France;

    CNRS, CEA, LTM, LETI, 17 Rue Martyrs, F-38054 Grenoble, France;

    CNRS, CEA, LTM, LETI, 17 Rue Martyrs, F-38054 Grenoble, France;

    CNRS, CEA, LTM, LETI, 17 Rue Martyrs, F-38054 Grenoble, France;

    CNRS, CEA, LTM, LETI, 17 Rue Martyrs, F-38054 Grenoble, France;

    CEA, LETI, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble, France;

    CEA, LETI, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble, France;

    STMicroelectronics, 850 Rue Jean Monnet, F-38926 Crolles, France;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    SiGe Siconi (R) preclean WET clean Grazing XPS; Source drain epitaxy;

    机译:SiGe Siconi(R)预清洁WET清洁Grazing XPS;源漏外延;

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