Tracking STI using an advanced optical metrology algorithm

摘要

Memory devices, such as DRAMs, have traditionally been manufactured using the local oxidation of silicon (LOCOS) process to achieve electrical isolation between memory cells. However, the method's creation of unused areas places serious limitations on its use in the deep submicron regime of next-and future-generation devices. One industry response to this limitation has been the adoption of shallow trench isolation (STI), but obtaining reliable measurements after STI and chemical-mechanical planarization (CMP) is problematic. The intent of CMP is to minimize topography across a wafer; however, a certain degree of topography is essential for edge contrast in optical overlay metrology.