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The Review of Cache Partitioning in Multi-core Processor

机译:多核处理器中的缓存分区综述

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摘要

With the development of microelectronics technology, Chip Multi-Processor (CMP) or multi-core design has become a mainstream choice for major microprocessor vendors. But in a chip-multiprocessor with a shared cache structure, the competing accesses from different applications degrade the system performance, resulting in non-optimal performance and non-predicting executing time. Cache partitioning techniques can exclusively partition the shared cache among multiple competing applications. In this paper, we first introduce the problems caused by Cache pollution in multicore processor structure; then present the different methods of Cachernpartitioning in multicore processor structure--categorizing them based on the different metrics.rnAnd finally, we discuss some possible directions for future research in the area.
机译:随着微电子技术的发展,芯片多处理器(CMP)或多核设计已成为主要微处理器供应商的主流选择。但是在具有共享缓存结构的芯片多处理器中,来自不同应用程序的竞争性访问会降低系统性能,从而导致性能不佳和执行时间无法预测。缓存分区技术可以专门在多个竞争应用程序之间划分共享缓存。在本文中,我们首先介绍多核处理器结构中缓存污染引起的问题;然后介绍了在多核处理器结构中进行高速缓存分区的不同方法-根据不同的指标对其进行分类。最后,我们讨论了该领域未来研究的一些可能方向。

著录项

  • 来源
    《Key Engineering Materials》 |2010年第2期|P.1223-1229|共7页
  • 作者单位

    School of Computer Science and Technology,Jilin University,Changchun,China Information Center,the State Tax Office of Jilin Province, Changchun,China;

    School of Computer Science and Technology,Jilin University,Changchun,China;

    School of Computer Science and Technology,Jilin University,Changchun,China;

    Jilin Communications Polytechnic,Changchun,China;

  • 收录信息
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    multi-core; Cache; IPC; miss rate monitor; Qos;

    机译:多核缓存;IPC;未命中率监视器;服务质量;

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