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首页> 外文期刊>Journal of supercomputing >Analytical performance assessment and high-throughput low-latency spike routing algorithm for spiking neural network systems
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Analytical performance assessment and high-throughput low-latency spike routing algorithm for spiking neural network systems

机译:尖峰神经网络系统的分析性能评估和高吞吐量低延迟尖峰路由算法

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Large-scale artificial neural networks (ANNs) have been used to mimic the information processing function of the brain. Spiking neural networks (SNNs) are a kind of ANN, which mimic real biological neural networks, conveying information through the communication of short pulses between neurons. Since each neuron in these networks is connected to thousands of others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, very low communication latency is also required. The 2D-NoC was used as a solution to provide a scalable interconnection fabric in large-scale parallel SNN systems. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. The combination of these two emerging technologies provides a new horizon for IC designs to satisfy the high requirements of low-power and small footprint in emerging AI applications. This paper first presents an analytical model to analyze the performance of different neural network topologies and compare it with a system-level simulation. Second, we present an architecture and a low-latency routing algorithm for spike traffic routing in 3D-NoC of spiking neurons (3DNoC-SNN). The 3DNoC-SNN is validated based on an RTL-level implementation, while area/power analysis is performed using 45-nm CMOS technology.
机译:大规模人工神经网络(ANN)已被用来模拟大脑的信息处理功能。尖峰神经网络(SNN)是一种ANN,它模仿真实的生物神经网络,通过神经元之间的短脉冲通信来传递信息。由于这些网络中的每个神经元都与数千个其他神经元相连,因此需要高带宽。此外,由于尖峰时间用于在SNN中编码信息,因此还需要非常低的通信延迟。 2D-NoC用作在大规模并行SNN系统中提供可伸缩互连结构的解决方案。 3D-IC作为解决互连瓶颈的潜在解决方案也引起了很多关注。这两种新兴技术的结合为IC设计提供了新的视野,以满足新兴AI应用中对低功耗和小尺寸的高要求。本文首先提出了一个分析模型,用于分析不同神经网络拓扑的性能并将其与系统级仿真进行比较。其次,我们为尖峰神经元的3D-NoC(3DNoC-SNN)中的尖峰流量路由提出了一种体系结构和一种低延迟路由算法。 3DNoC-SNN基于RTL级实现进行了验证,而面积/功耗分析则使用45纳米CMOS技术进行。

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