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Elliptic Curve Cryptography hardware accelerator for high-performance secure servers

机译:椭圆曲线密码学硬件加速器,用于高性能安全服务器

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摘要

Security threats affecting electronics communications in the current world make necessary the encryption and authentication of every transaction. The increasing levels of security required are leading to an overload of transaction servers due to cryptographic tasks. In this paper, a hardware-implemented coprocessor for Elliptic Curve Cryptography operations is presented. This coprocessor enables the acceleration of secure services and can be implemented in the last generations FPGA, thus allowing to host in the same chip a software secure web/database server and the cryptographic coprocessor. Obtained results show advantages of the proposed solution when compared to software implementations and classical acceleration using graphics processing units. Moreover, the proposed cryptographic coprocessor presents improvements over other hardware implementations when area, performance and scalability are considered. The developed crypto-processor has been implemented in a xc7z020clg484-1 device from Xilinx, taking advantage of the synergy provided by the ARM microprocessors and the programmable logic for hardware implementations included in the device. This design requires only 9852 LUTs, while providing 8930 scalar-point operations per second when operating at 50 MHz, with a power consumption of 0.42 W.
机译:当前,影响电子通讯的安全威胁使得必须对每笔交易进行加密和认证。所需的不断提高的安全性由于加密任务而导致事务服务器超负荷。本文提出了一种用于椭圆曲线密码学操作的硬件实现的协处理器。该协处理器可以加快安全服务的速度,并且可以在最后几代FPGA中实现,从而可以在同一芯片中托管软件安全的Web /数据库服务器和密码协处理器。与软件实现和使用图形处理单元的经典加速相比,获得的结果表明了所提出解决方案的优势。而且,当考虑面积,性能和可伸缩性时,提出的密码协处理器提出了对其他硬件实现的改进。 Xilinx的xc7z020clg484-1器件已实现了开发的加密处理器,并利用了ARM微处理器提供的协同作用以及该器件中包含的硬件实现的可编程逻辑。该设计仅需要9852个LUT,而在50 MHz的频率下运行时,每秒可提供8930个标量点运算,功耗为0.42W。

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