A High Speed Reconfigurable Firewall Based On Parameterizable FPGA-based Content Addressable Memories

摘要

A technique for implementing a Content Addressable Memory (CAM) on an FPGA is described. The CAM is highly parameterizable, allowing varying memory depths and oper- ations to be implemented depending upon the requirements of the target application. The application of the CAM is then demonstrated by using it in the core of a network firewall application, where it is used in a pipeline Ip packet detection algorithm.