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机译:用于高性能QueueCore处理器体系结构的自然指令级并行感知编译器
School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, Fukushima-ken, Aizu-Wakamatsu-shi 965-8580, Japan;
School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, Fukushima-ken, Aizu-Wakamatsu-shi 965-8580, Japan;
School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, Fukushima-ken, Aizu-Wakamatsu-shi 965-8580, Japan,IBM Tokyo Research Laboratory, 1623-14 Shimotsuruma. Yamato-shi, Kanagawa-ken 242-8502, Japan;
School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, Fukushima-ken, Aizu-Wakamatsu-shi 965-8580, Japan;
instruction level parallelism; compiler; queue processor; high-performance;
机译:用于高性能QueueCore处理器体系结构的自然指令级并行感知编译器
机译:CAIRO:用于启用注视级卸载的编译器辅助技术
机译:架构和编译器技术,可降低高性能微处理器的能耗
机译:应用程序特定指令集处理器中的编译器辅助架构支持对应用程序代码完整性监视
机译:用于降低高性能微处理器能耗的体系结构和编译器技术。
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机译:针对特定应用指令集处理器中的程序代码完整性监控的编译器辅助架构支持*