New Methodology for Simulation of Soft Errors in Digital Processors

摘要

Development and implementation are presented of a new fault injection technique for error rate prediction of processor-based digital architectures operating under radiation. Bit flips are injected in potentially sensitive memory locations concurrently with execution of a program. The error rate derived from those fault injection experiments and the underlying cross section of the studied processor will allow the cross section estimation of this circuit running a given program. A comparative analysis of experimental results issued from both soft error injection and ground testing under radiation performed on a board built around a microprocessor demonstrates the efficiency of this new technique to predict the error rate of an application.