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Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System

机译:H.264系统中嵌入式SRAM存储器的基于优先级的纠错码(ECC)

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With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.
机译:通过积极的电源电压缩放,H.264系统的嵌入式存储器中的SRAM位单元故障会导致视频质量显着下降。纠错编码(ECC)已被广泛用于嵌入式存储器中以纠正这些故障,但是,常规ECC方法并未考虑存储在存储器中数据的重要性方面的差异。本文提出了一种基于优先级的ECC(PB-ECC)方法,其中较重要的高阶位(HOB)比不太重要的低阶位(LOB)具有更高的优先级,因为人类视觉系统对LOB错误的敏感度较低。还提出了有关PB-ECC方案的纠错能力及其在H.264系统中导致的峰值信噪比(PSNR)降级的数学分析,以帮助设计人员确定较高和较高比特的比特分配。嵌入式存储器的低优先级段。我们使用90 nm CMOS技术设计和实现了三种PB-ECC案例(仅限汉明,仅BCH和混合PB-ECC)。与传统的ECC方法相比,在900 mV或更低的电源电压下,实验结果可提供高达6.0 dB的PSNR改善,并且电路面积更小。

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