机译:基于混合线性代数/ FFT核的高效多核浮点FFT架构
Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA;
Texas Advanced Computing Center, The University of Texas at Austin, Austin, TX, USA;
Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA;
Fast Fourier Transform; Floating point Multicore; Memory hierarchy; Power efficiency; Low power design; Linear algebra;
机译:用于浮点FFT计算的面积和能源效率混合架构
机译:基于多操作数加法器的面积有效的浮点FFT蝶形架构
机译:基于单侧二叉树分解的可重构4GS / s节能浮点FFT处理器设计与实现
机译:基于配置内存的8点FFT动态粗粒度可重配置多核架构
机译:分层内存和多核架构上的FFT自适应动态调度
机译:超高效的1024点内存中FFT处理器
机译:HC-FFT:高度可配置和高效的FPGA实现FFT