Bimodal packet aware scheduling for an OFDMA based on-chip RF interconnect

摘要

Abstract As massive microprocessors with thousands of cores are on the horizon, using Radio Frequency (RF) or state-of-the-art nanophotonic on-chip interconnects appears as a solution to cope with current latency constraints. Due to their reliance on numerous static circuitry to generate communication channels, proposed architectures cannot rearbitrate the available bandwidth to on-chip nodes according to instantaneous traffic demands. In this paper, we present an Orthogonal Frequency Division Multiple Access (OFDMA) based wired on-chip RF interconnect as an effective reconfigurable and broadcast capable modulation. A hierarchical 2048-core CMP architecture is explained along with its hybrid cache coherency mechanism. Based on this novel architecture, we introduce an innovative bandwidth arbitration mechanism which allocates more bandwidth to cache-line carrying long packets without requiring extra signaling overhead. Exploiting broadcast capability and effective reconfigurability, we show that this bimodal packet aware communication infrastructure can provide up to 10 ×  less average latency compared to a static counterpart under certain circumstances. Highlights • An OFDMA based RF interconnect is presented in the scope of our project. • A novel bandwidth scheduling for bimodal coherence packet lengths is developed. • Analytical expressions for estimated packet latencies are derived. • The novel necessary digital infrastructure without overhead is presented in detail. • Latency can be decreased up to 10 times compared to conventional scheduling.