DSPONE48: A methodology for automatically synthesize HDL focus on the reuse of DSP slices

摘要

This work proposes a methodology to synthesize arithmetic operations maximizing the reuse of the DSP48E1 blocks presented in the new reconfigurable architectures. The input for DSP0NE48 is a VHDL code without any reference to the FPGA hardware resources. This input code is modified, so the synthesis tool is able to implement it with DSP slices. In order to achieve this objective we use DSP block instantiation templates and we encourage the use of SIMD mode within the DSP block. This methodology replaces automatically the most common arithmetic operations by their equivalents on DSP slices. The methodology guarantees that the new code preserves the functionality and the number of execution cycles of the original design. Experimental results, on a Virtex 7 FPGA, show that the designs obtained by DSPONE48 use less DSPs than those obtained automatically by Xilinx ISE or Vivado. Moreover, these designs have lower area and higher frequency.