Delay analysis and optimization for inter-core interference in real-time embedded multicore systems

摘要

The Worst Case Execution Time (WCET) is one of the most important performance metrics in real-time systems. With multi-core architectures becoming a trend in real-time systems, the WCET analysis is of great challenge, since multiple cores accessing shared hardware resources, such as cache and bus, may result in significant interference on them. In this paper, we propose a finer grained approach to analyze the inter-core interference(bank conflict and bus access interference) on multi-core platforms with the interference-aware bus arbiter(IABA) and bank-column cache partitioning, and our approach can reasonably estimate interference delays biased on request timing. Moreover, we optimize bank-to-core mapping to reduce the interference delays, and develop an algorithm for finding the best bank-to-core mapping. The experimental results show that our interference analysis approach can improve the tightness of interference delays by 18.36% on average compared to Upper Bound Delay(UBD) approach, and the optimized bank-to-core mapping can achieve the WCET improvement by 8.93% on average.