Introducing Fault-Tolerance to Multiple-Valued Logic with Error-Correcting Decision Diagrams

摘要

Error-correcting decision diagrams are a new method of providing fault-tolerance into logic circuits. By combining decision diagrams, which are an efficient way of representing switching functions, and error-correcting codes to obtain error-correcting decision diagrams, fault-tolerance is introduced already to the representations of switching functions. Depending on the technology, the implementation of these diagrams is straightforward and the obtained diagrams directly determine the layout of the final circuit. Thus, error-correcting decision diagrams are efficient robust representations of functions and require no additional checker circuitry when implemented on the circuit level. In this paper, we introduce error-correcting decision diagrams for multiple-valued functions and analyze their fault-toierance. We consider error-correcting decision diagrams for multiple-valued functions generated with codes in the Hamming and the Lee metric. The fault-tolerance analysis shows that the robust diagrams have a significantly higher probability of correct outputs than corresponding non-redundant diagrams, while better error-correcting properties increase the complexity of the designs. However, we demonstrate that even with moderate increments in complexity it is possible to obtain significantly increased probabilities of correct outputs.