VHDL High Level Design of Digital Systems with HLS/BIT

摘要

The authors discuss in this paper how to construct the VHDL design environment based on the experiences of developing a VHDL EDA system HLS/BIT. Being a synthesis-based VHDL design system, HLS/BIT starts from behavioral level And synthesizes the circuit through a series of highly-automated tasks. The design Process of HLS/BIT is introduced with a specific design example.