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A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory

机译:嵌入式系统的新型存储器结构:灵活的顺序和随机存取存储器

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The on-chip memory performance of embedded systems directly affects the system designers' decision about how to allocate expensive silicon area. A novel memory architecture, flexible sequential and random access memory (FSRAM), is investigated for embedded systems. To realize sequential accesses, small "links" are added to each row in the RAM array to point to the next row to be prefetched. The potential cache pollution is ameliorated by a small sequential access buffer (SAB). To evaluate the architecture-level performance of FSRAM, we ran the Mediabench benchmark programs on a modified version of the SimpleScalar simulator. Our results show that the FSRAM improves the performance of a baseline processor with a 16KB data cache up to 55%, with an average of 9%; furthermore, the FSRAM reduces 53.1% of the data cache miss count on average due to its prefetching effect. We also designed RTL and SPICE models of the FSRAM, which show that the FSRAM significantly improves memory access time, while reducing power consumption, with negligible area overhead.
机译:嵌入式系统的片上存储器性能直接影响系统设计人员有关如何分配昂贵的硅面积的决定。针对嵌入式系统,研究了一种新颖的存储体系结构,即灵活的顺序和随机存取存储器(FSRAM)。为了实现顺序访问,将较小的“链接”添加到RAM阵列的每一行,以指向要预取的下一行。较小的顺序访问缓冲区(SAB)可减轻潜在的缓存污染。为了评估FSRAM的体系结构级性能,我们在SimpleScalar模拟器的修改版上运行Mediabench基准程序。我们的结果表明,FSRAM通过将16KB数据高速缓存提高到55%(平均为9%)来提高基准处理器的性能。此外,由于其预取效果,FSRAM平均减少了53.1%的数据高速缓存未命中计数。我们还设计了FSRAM的RTL和SPICE模型,这表明FSRAM显着改善了存储器访问时间,同时降低了功耗,而面积开销却可以忽略不计。

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