Noise-Coupled Time-Interleaved Delta-Sigma Modulator with Reduced Hardware Complexity

摘要

Developing an analog-to-digital converter (ADC) based on the time-interleaved delta-sigma modulator (TIDSM) is an appropriate technique to attain high-speed ADCs. TIDSMs can be successfully accomplished with the aid of developing the block digital filtering (BDF) method. In this approach, M mutually cross-connection delta-sigma modulators are used, whereby each one of them operates at a sampling rate of f(s), leading to an effective sampling rate of M * f(s). In this study, a novel structure is proposed based on the Noise Coupled time-interleaved delta-sigma modulator (NC-TIDSM) with reduced hardware complexity. This structure not only increases the overall noise transfer function (NTF) order, but also reduces the hardware element counts. The simulation results demonstrate that the SNDRs of the first-order two-channel and four-channel NC-TIDSM with reduced hardware are 13 and 15 dB better than those of their BDF technique counterparts; also, the SNDR of the second-order two-channel NC-TIDSM with reduced hardware is 8 dB better than that of their BDF technique counterpart; also, the hardware element quantities are reduced dramatically. Moreover, some practical challenges such as the finite op-amp's gain and mismatching effects that directly affect the circuit implementation of the proposed structure have been described. Furthermore, the hardware complexity of the proposed structures is reduced considerably in comparison to that of the BDF technique with the NC-TIDSM structure.