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A New CPFSK Demodulation Approach for Software Defined Radio

机译:用于软件无线电的新型CPFSK解调方法

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This paper proposes a new coherent Frequency-Shift Keying (FSK) demodulation technique for software defined radio platform, based on a new Digital Phase Locked Loop (DPLL) architecture. The proposed DPLL addresses the frequency dependence on classic DPLL architectures found in the literature. In classical approaches, the loop filter constants are dependent on the frequency level of the FSK transmitted symbols. The proposed approach applies a simpler feedback loop, with a single integrator and a phase detector architecture based on the small-angle approximation sin(beta) approximate to beta, which resulted in a DPLL totally independent of frequency. The proposed demodulator has been implemented in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) and evaluated for continuous-phase frequency shift keying (CPFSK) and Gaussian minimum shift keying (GMSK) signals. For CPFSK signals, the demodulator has been evaluated for 2, 4 and 8 frequency levels, with modulation indexes 0.5, 0.25 and 0.125, respectively. For evaluation of GMSK signals, several Gaussian filter bandwidths were considered. In addition, a brief analysis for 2-CPFSK and GMSK is presented over multipath and carrier frequency offset. Results show that the proposed method presents a significantly reduced bit error rate when compared to other coherent methods presented in the literature.
机译:本文基于一种新的数字锁相环(DPLL)架构,为软件定义的无线电平台提出了一种新的相干频移键控(FSK)解调技术。提出的DPLL解决了文献中发现的经典DPLL体系结构的频率依赖性。在经典方法中,环路滤波器常数取决于FSK传输符号的频率水平。所提出的方法采用了更简单的反馈环路,具有单个积分器和基于近似于beta的小角度近似sinβ的鉴相器架构,从而导致DPLL完全独立于频率。拟议的解调器已在超高速集成电路(VHSIC)硬件描述语言(VHDL)中实现,并对连续相频移键控(CPFSK)和高斯最小频移键控(GMSK)信号进行了评估。对于CPFSK信号,已对解调器的2、4和8个频率水平进行了评估,调制指数分别为0.5、0.25和0.125。为了评估GMSK信号,考虑了几个高斯滤波器带宽。此外,还针对多路径和载波频率偏移对2-CPFSK和GMSK进行了简要分析。结果表明,与文献中提出的其他相干方法相比,所提出的方法显着降低了误码率。

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