A Capacitor-Splitting Switching Scheme with Low Total Power Consumption for SAR ADCs

摘要

A low-power capacitor-splitting switching algorithm for successive approximation register (SAR) and analog-to-digital converters (ADCs) is proposed. To reduce the total power consumption, it does not require reset energy, which accounts for a large proportion. Besides, energy-effcient one-side double-level switching technique is also utilized from the forth bit cycle. Thus, the proposed switching algorithm requires 26.54 CVREF2 total switching energy, 16.75% less over the tri-level one. Due to the capacitor-splitting structure, it also shows good linearity performance.