High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

摘要

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-mu m CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20MHz UGF and 145 dB CMRR @ 1.2V supply voltage while the power consumption is 400 mu W which makes it suitable for low-voltage applications.