Memory-efficient architecture of 2-D lifting-based discrete wavelet transform

摘要

This article presents new hardware architectures to address critical issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding modes) lifting-based discrete wavelet transform (LDWT) for Motion-JPEG2000. The massive requirement of transpose memory is the most critical for LDWT. The proposed architecture can support high-resolution videos and reduce the internal memory requirement significantly. In our LDWT approach, the signal flow is revised from row-wise only to mixed row- and column-wise, and a new architecture, called interlaced read scan architecture (IRSA), is used to reduce the transpose memory. By the IRSA approach, the transpose memory size is only 2N or 4N (5/3 or 9/7 mode) for an N × N DWT. Besides, the proposed 2-D LDWT operates with parallel and pipelined schemes to increase the operation speed. It can be applied to real-time visual operations such as JPEG2000 and Motion-JPEG2000.View full textDownload full textKeywordslifting scheme, discrete wavelet transform (DWT), low internal memory, interlaced read scan architecture (IRSA)Related var addthis_config = { ui_cobrand: "Taylor & Francis Online", services_compact: "citeulike,netvibes,twitter,technorati,delicious,linkedin,facebook,stumbleupon,digg,google,more", pubid: "ra-4dff56cd6bb1830b" }; Add to shortlist Link Permalink http://dx.doi.org/10.1080/02533839.2011.577601