As test data continues to grow quickly, test cost also increases. For the sake of decreasing the test cost, this article presents a new data dependency compression scheme for large circuit which is based on multiple scan chains. We propose new compression architecture with fixed length for running tests. In results, when the complexity of a VLSI circuit is growing, the number of input pins for testing is very low. Since test data in power aware is not changed frequently, we use a selector to filter the unnecessary status and buffers to hold the back data. We also propose a new algorithm to assign multiple scan chains and an improved linear dependency compute method to find the hidden dependency between scan chains. Experimental results show that the proposed method can reduce both test data volume and shift-in power.View full textDownload full textKeywordsscan based testing, low power testing, test data compression, design for testability (DfT)Related var addthis_config = { ui_cobrand: "Taylor & Francis Online", services_compact: "citeulike,netvibes,twitter,technorati,delicious,linkedin,facebook,stumbleupon,digg,google,more", pubid: "ra-4dff56cd6bb1830b" }; Add to shortlist Link Permalink http://dx.doi.org/10.1080/02533839.2011.576498
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机译：随着测试数据的持续快速增长，测试成本也随之增加。为了降低测试成本，本文提出了一种基于大型扫描链的大型电路数据依赖压缩方案。我们提出了具有固定长度的新压缩架构，用于运行测试。结果，当VLSI电路的复杂度增加时，用于测试的输入引脚的数量非常少。由于省电模式下的测试数据不会经常更改，因此我们使用选择器来过滤不必要的状态，并使用缓冲区保存返回的数据。我们还提出了一种分配多个扫描链的新算法，以及一种改进的线性相关性计算方法来查找扫描链之间的隐藏依赖性。实验结果表明，该方法可以减少测试数据量和移入功率。查看全文下载关键字基于扫描的测试，低功耗测试，测试数据压缩，可测试性设计（DfT）相关var addthis_config = {ui_cobrand：“ Taylor ＆Francis Online”，services_compact：“ citeulike，netvibes，twitter，technorati，delicious，linkedin，facebook，stumbleupon，digg，google，更多”，发布号：“ ra-4dff56cd6bb1830b”};添加到候选列表链接永久链接http://dx.doi.org/10.1080/02533839.2011.576498
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