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Novel low-power bus invert coding methods with crosstalk detector

机译:具有串扰检测器的新型低功耗总线反相编码方法

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In System-on-a-Chip designs, crosstalk effects cause serious problems, such as wire propagation delay, noise, and power dissipation. In this article, we propose two new bus coding methods to reduce the dynamic power dissipation and wire propagation delay on buses efficiently. The proposed methods reduce both the dynamic power dissipation and wire propagation delay more than the existing bus coding methods do. Experimental results show that the crosstalk detector bus invert (CDBI) method reduces coupling activity to 25.7% from 36.4% and switching activity to 4.5% from 8.5% on 8-bit to 32-bit data buses. It reduces total power dissipation more than the other bus coding methods when a load capacitance is more than 0.3 pF/bit with UMC 0.09-µm CMOS technology. The enhanced CDBI (ECDBI) coding method reduces coupling activity to 28.4% from 38.4% and switching activity to 10.1% from 14% on 8-bit to 32-bit data buses. It reduces total power dissipation more than the other bus coding methods when a load capacitance is more than 0.2 pF/bit with UMC 0.09-µm CMOS technology. For a 0.8 pF/bit load capacitance, both the proposed methods reduce total power use by 19.3-30.9% when systems are implemented with UMC 0.09-µm CMOS technology. Similarly, both the proposed methods also reduce total power consumption more than the other bus coding methods with TSMC 0.18-µm CMOS technology. Meanwhile, the CDBI and the ECDBI schemes reduce total propagation delay up to 31.8% and 34.2%, respectively, on 32-bit data buses.View full textDownload full textKeywordsbus coding, low-power, coupling activity, switching activity, system on a chipRelated var addthis_config = { ui_cobrand: "Taylor & Francis Online", services_compact: "citeulike,netvibes,twitter,technorati,delicious,linkedin,facebook,stumbleupon,digg,google,more", pubid: "ra-4dff56cd6bb1830b" }; Add to shortlist Link Permalink http://dx.doi.org/10.1080/02533839.2011.553030
机译:在片上系统设计中,串扰效应会引起严重的问题,例如导线传播延迟,噪声和功耗。在本文中,我们提出了两种新的总线编码方法,以有效降低总线上的动态功耗和导线传播延迟。与现有的总线编码方法相比,所提出的方法减少了动态功耗和导线传播延迟。实验结果表明,串扰检测器总线反相(CDBI)方法可将8位至32位数据总线上的耦合活动从36.4%降低到25.7%,将开关活动从8.5%降低到4.5%。当采用UMC 0.09-µm CMOS技术的负载电容大于0.3pF /位时,它比其他总线编码方法更能降低总功耗。增强的CDBI(ECDBI)编码方法可将8位到32位数据总线上的耦合活动从38.4%降低到28.4%,将切换活性从14%降低到10.1%。当采用UMC 0.09-µm CMOS技术的负载电容大于0.2pF /位时,它比其他总线编码方法更能降低总功耗。对于0.8pF /位的负载电容,当系统采用UMC 0.09-µm CMOS技术实现时,两种建议的方法都可将总功耗降低19.3-30.9%。同样,与台积电(TSMC)0.18-µm CMOS技术相比,这两种建议的方法还比其他总线编码方法减少了总功耗。同时,CDBI和ECDBI方案在32位数据总线上分别将总传播延迟分别降低了31.8%和34.2%。查看全文下载全文关键词总线编码,低功耗,耦合活动,交换活动,片上系统相关var addthis_config = {ui_cobrand:“泰勒和弗朗西斯在线”,servicescompact:“ citeulike,netvibes,twitter,technorati,delicious,linkedin,facebook,stumbleupon,digg,google,更多”,发布号:“ ra-4dff56cd6bb1830b”};添加到候选列表链接永久链接http://dx.doi.org/10.1080/02533839.2011.553030

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