Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications

摘要

The DC/AC performances of sub-7-nm node nanosheet FETs (NSFETs) with different NS widths (W-NS) and number of NSs (N-NS) were investigated after fine calibration to 10-nm node fin-shaped FETs (FinFETs). A smaller W-NS improves the short-channel effects but decreases the effective widths and the on-state currents (I-on). A higher N-NS is beneficial for improving I-on by reducing source/drain (S/D) resistance, but longer carrier paths for the NS channels far from the S/D contacts act as a bottleneck for improvement of DC performance. Instead, gate capacitances increase constantly at the same rate as increase in N-NS because both intrinsic and parasitic capacitances increase. As a result, sub-7-nm node NSFETs have minimum RC delay for a wide W-NS of 44 nm and N-NS of 2 and 3 for p- and n-type, respectively, outperforming 10-nm node FinFETs for standard and high-performance applications. (C) 2019 The Japan Society of Applied Physics