首页> 外文期刊>Japanese journal of applied physics >Effect of Oxidation Amount on Gradual Switching Behavior in Reset Transition of AI/TiO_2-Based Resistive Switching Memory and Its Mechanism for Multilevel Cell Operation
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Effect of Oxidation Amount on Gradual Switching Behavior in Reset Transition of AI/TiO_2-Based Resistive Switching Memory and Its Mechanism for Multilevel Cell Operation

机译:氧化量对基于AI / TiO_2的电阻开关记忆复位转变中的逐步开关行为的影响及其多级电池工作机理

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摘要

To analyze and explain the gradual reset switching property of the bipolar switching resistive random access memory (RRAM) for multilevel cell (MLC) operation, the effect of the amount of plasma oxidation on the gradual reset switching behavior of the AI/TiO_2-based RRAM cell structure is investigated. The device that undergoes plasma oxidation in a shorter time has a better ON/OFF current (I_(ON)I_(OFF)) ratio and shows increased ON current (I_(ON)). The device that undergoes long plasma oxidation occasionally shows the step reset switching behavior because of the thick conductive filament formation in the ON state. This is clearly explained by the different conduction mechanisms during the ON state.
机译:为了分析和解释用于多级单元(MLC)操作的双极开关电阻型随机存取存储器(RRAM)的逐渐复位开关特性,等离子氧化量对基于AI / TiO_2的RRAM逐渐复位开关行为的影响研究细胞结构。在较短时间内进行等离子体氧化的设备具有更好的开/关电流(I_(ON)I_(OFF))比,并显示出增加的开电流(I_(ON))。由于在导通状态下会形成厚的导电丝,经受长时间等离子体氧化的设备有时会显示阶跃复位开关行为。这可以通过导通状态期间的不同传导机制清楚地解释。

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  • 来源
    《Japanese journal of applied physics》 |2012年第4issue2期|p.04DD16.1-04DD16.5|共5页
  • 作者单位

    Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, Seoul 151-742, Republic of Korea,DRAM Process Architecture Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd., Hwasung, Gyeonggi 445-701, Republic of Korea;

    Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, Seoul 151-742, Republic of Korea,DRAM Process Architecture Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd., Hwasung, Gyeonggi 445-701, Republic of Korea;

    Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, Seoul 151-742, Republic of Korea;

    DRAM Process Architecture Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd., Hwasung, Gyeonggi 445-701, Republic of Korea;

    Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, Seoul 151-742, Republic of Korea;

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