Micro Synchronization Mechanisms on a Massively Parallel Computer

摘要

This paper presents a micro synchronization mechanism for massively parallel computers. The mechanism is based on a message processing scheme, and realizes both low implementa- tion cost and high performance of micro synchronization. Macro synchronization, as a barrier, is also performed efficiently using combination of that mechanism with software control. In this paper, we show the micro synchronization mechanism on RWC-1. Evaluations of its hardware cost and basic performance are also described.