An application of Hopfield networks to worst-case power analysis of RT-level VLSI systems

摘要

This paper presents a technique for analyzing the power behavior of digital VLSI systems. The algorithm initially translates the RT-level description of the design into an Hopfield network. Symbolic simulation is then performed on such a network and the energy dissipated at each simulation step is accumulated. Upon completion, a worst-case measure of the power dissipated by the VLSI system is available. The experiments run on several benchmark examples show the feasibility of the method.