Fast-squarer circuits using 3-bit-scan without overlapping bits

摘要

This paper presents a novel technique to design fast-squaring circuits. The proposed approach speeds up squaring operations combining the 3-bit scan without overlapping bits and the folding technique. Several hardware implementations of squarer circuits designed as described here are characterized for several operand wordlengths. Obtained results demonstrate that, using the ST 90 nm IV CMOS technology, a 32-bit squarer exploiting the novel way of generating partial products reaches a 769 MHz running frequency, dissipates less than 19.3 mW on average and occupies ~91000um~2 of silicon area. Copyright