Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array

摘要

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image-processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low-power consumption. An integrated circuit with proof-of-concept array of 24 x 60 cells has been fabricated in a 0.35 urn three-metal CMOS process and tested. Occupying only 16 × 8μm~2 the binary wave-propagation cell is designed to be used as a co-processor in general-purpose processor-per-pixel arrays intended for focal-plane image processing. The results of global operations such as object reconstruction and hole filling are presented.