Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2~m)

摘要

In this paper, a novel architecture for a versatile polynomial basis multiplier over GF(2~m) is presented. The proposed architecture provides an efficient execution of the Most Significant Bit (MSB)-First, bit-serial multiplication for different operand lengths. The main advantages of the proposed architecture are (a) its flexibility on arbitrary Galois field sizes, (b) its hardware simplicity which results in small area implementation, (c) low power consumption by employing the gated clock technique (d) improvement of maximum clock frequency due to the lessening of critical path delay. These abilities are achieved by means of utilizing a row of tri-state buffers and some control signals along with the (MSB)-first multiplier in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity.