High-level test synthesis: a survey

摘要

This paper surveys the various high-level design for testability and synthesis for testability methods that have been proposed in the last decade. We begin with a description of high-level synthesis methods which target the ease of subsequent gate-level sequential test generation. Then we describe high-level synthesis methods which target built-in lf-test (BIST) and hierarchical testability. Thereafter, we describe register-transfer level testability techniques that target gate-level test generation, BIST and hierarchical testability. We then describe some high-level test generation methods in brief.