A GA with heuristic-based decoder for IC floorplanning

摘要

In this paper, we describe a genetic algorithm wih heurisic-based layout decoder (GAHD) for floorplanning in IC design. The basic idea is to make use of a GA to search for an optimal arrangement of circuit modules on a pre-specified layout area. To achieve a GA that is efficient in floorplanning, we employ a technique to systematically determine suitable weighting coefficients of the search objectie in deriving a suitablke objective function. For each arrangement of flexible modules derived by the GA, the aspect ratios of all the modules are fixed such that the modules when fully placed and routed will yield a floorplan that is efficent in terms of area and wirelength. For this purpose, we designed a heuristic-based layout decoder for determining the optimal aspec raio and orientation of each module. Our results show improvement over otehr reported floorplanning algorithms based on simulations of the AMI33 benchmark problem.