Area and power efficient hard multiple generator for radix-8 modulo 2~n - 1 multiplier

摘要

In this paper, we introduce an area and power efficient algorithm to design a hard multiple generator for radix-8 modulo 2(n) - 1 multiplier, which is based on parallel prefix computation of carry propagate. Only odd carry is used to generate hard multiple bits. The proposed architecture uses [log(2)n]-2 prefix level with n/2 prefix operators. The Post-synthesis result of proposed architecture shows 27.91%-36.89%, 9.64%-22.45% and 0.02%-88.62% of saving in area, power and PDP, respectively while post-layout result shows 27.66%-36.88%,14.45%-33.53% and 11.40%-81.11% of saving in area, power and PDP, respectively.