Test Generation for Sequential Circuits under IDDQ Testing

摘要

This paper presents a test generation method for sequential circuits under IDDQ testing environment and the iden- tification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short compr- tational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.