Transistor Leakage Fault Diagnosis for CMOS Circuits

摘要

This paper presents a new methodology for diagnosing transistor leakage faults in a CMOS circuit by using both I_DDQ and logic value information. A hierarchical procedure is used to identify and delete impossible fault candidates efficiently and a procedure is employed to generate diagnostic tests for improving diagnostic resolution. A novel approach for handling the intermediate output voltage of a faulty gate is used in new methods for fault simulation and diagnostic test genera- tion based on primary output values. Experimental results on ISCAS'85 circuits show the effectiveness of the proposed metho- dology.