Transistor Leakage Fault Diagnosis with I_DDQ and Logic Information

摘要

This paper proposes a new methodology for diagnosing transistor leakage faults with information on I_DDQ and logic values at primary output lines. A hierarchical approach is proposed to identify the faults that do not exist in the circuit through comparing their I_DDQ and logic behaviors predicted by simulation with observed responses. Several techniques for handling intermediate faulty voltages in fault simulation are also proposed. Further, an approach is proposed to generate diagnos- tic vectors based on I_DDQ information.