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A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier

机译:可轻松测试的高速乘法器的C可测试4-2加法器树

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A C-testable 4-2 adder tree for an easily testable highspeed multiplier is proposed, and a recursive method for test generation is shown. By using the specific patterns that we call 'alternately inverted patterns,' the adder tree, as well as partial product generators, can be tested with 14 patterns regardless of its operand size under the cell fault model. The test patterns are easily fed through the partial product generators. The hardware overhead of the 4-2 adder tree with partial product generators for a 64-bit multiplier is about 15%. By using a previously proposed easily testable adder as the final adder, we can obtain an easily testable high-speed multiplier.
机译:提出了一种可测试的高速乘法器的C可测试的4-2加法器树,并给出了一种用于测试生成的递归方法。通过使用我们称为“交替倒置模式”的特定模式,可以用14种模式测试加法器树以及部分乘积生成器,而不管其在单元故障模型下的操作数大小如何。测试图案很容易通过部分产品生成器馈入。具有用于64位乘法器的部分乘积生成器的4-2加法器树的硬件开销约为15%。通过使用先前提出的易于测试的加法器作为最终加法器,我们可以获得易于测试的高速乘法器。

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